1. Field of the Invention
The present invention relates to a MOS type semiconductor device and manufacturing method thereof. More particularly, the invention relates to a complementary MOS (CMOS) type field-effect transistor (FET).
2. Description of the Related Art
In the prior art, there is known an Static Random Access Memory (SRAM) as a device in which CMOS type field-effect transistors (FETs) are applied to its memory cells. In the case where CMOS FETs are applied to a memory cell of the SRAM, a problem will arise with the resistance to soft errors (see, e.g. Jpn. Pat. Appln. KOKAI Publication No. 6-310683).
Normally, a soft error rate (SER) becomes higher as the scaling of FETs increases. In particular, in the generation after the 90 nm technology node, the increase in SER poses a serious problem.
As mentioned above, in the SRAM in which CMOS FETs are applied to the memory cell, the resistance to soft errors is a problem to be solved. It is expected that the SER will rise with the increase in scaling of FETs. It is very difficult, however, to decrease the SER without degrading the circuit performance or increasing the chip area.